1. Technical Field
Embodiments of the present disclosure may generally relate to a delay control device and method for the same, and more particularly to a technology for compensating for a delay difference of a delay locked loop (DLL).
2. Related Art
In a semiconductor memory device designed to operate by synchronizing with an external clock signal, if an internal clock signal is delayed more than an external clock signal by a predetermined time, high frequency performance of the semiconductor memory device deteriorates. Specifically, after the external clock signal is applied to the semiconductor memory device, a data output time (i.e., an output data access time (tAC)) is elongated.
Therefore, in order to prevent deterioration of the high-frequency performance of the semiconductor memory device, a circuit for accurately synchronizing the phase of an internal clock signal to the phase of an external clock signal is needed. For this purpose, a delay locked loop (DLL) is used.
The delay locked loop (DLL) controls delay of a delay loop using a replica. The replica is a copy of a clock path or a data path, and the amount of delay of the delay loop is determined according to the amount of replica delay.
The delay locked loop (DLL) copies a real clock path delay as a replica delay. The replica delay and the real clock path delay may be changed according to PVT (Process, Voltage, Temperature) or the like. In this case, the degree of twist (or dislocation) between the clock signal and a data strobe signal (DQS) is changed according to the process, the voltage, and the temperature (PVT), respectively.